The present invention relates broadly to an error detection apparatus, and in particular to a pipelined error detection and correction apparatus utilizing a programmable address trap.
It is well known that the reliability of data stored in memory devices can be significantly increased through the use of error detection and correction (EDC) techniques. Typically, the devices to implement these techniques can detect and flag all single, double, and some more than two bit errors. Single bit errors (within a word) can also be corrected. These error detection and correction techniques can be used not only for fault detection but also for fault isolation. In order to isolate a fault to the memory chip level, it is necessary to know not only that an error has occurred but also whether it was a single or multiple bit error and at what memory address it occurred. However, the addition of error detection and correction circuits create and/or present the following problems:
A. Loading - The addition of error detection and correction devices increases the load on the output of the memory devices and therefore the device access time. This problem is typically solved by adding buffer devices. This invention solves the problem by adding a separate input port for the memory devices which presents a minimum load without increasing the component count.
B. Speed - Newer and faster memory devices require faster error detection and correction devices. Currently available error detection and correction devices were designed for applications where they are tightly coupled to the central processing unit (CPU) and therefore do not take advantage of speed enhancements permitted by a pipelined error detection and correction device. This invention makes use of clocked input and output pipelined registers and can perform a correction in approximately 25 nanoseconds (typical at 25 degrees C.). This can be achieved by using VHSIC CMOS technology. At this speed all data can be clocked through the error detection and correction device pipeline registers and the data flow is not interrupted to perform an error correction operation.
C. Fault Isolation - Fault isolation can be simple in a memory that is tightly coupled to a central processing unit, but can be difficult when the memory array is being accessed over a system bus which interfaces the memory array to the central processing unit through two bus interface units. In such a case, the central processing unit does not know the memory address of the error. This invention solves the problem by having programmable error flag, check bit, and address traps which the central processing unit can read via the data port.
D. Testing - Adding an error detection and correction device to the memory system now requires a test method to validate the proper operation of the error detection and correction device. Some current error detection and correction devices have diagnostic modes but their ability to provide fault isolation features is limited. This invention incorporates the typical diagnostic features but also has data paths that permit wrap tests of the address and check bits.
E. Device Count - Additional devices need to be added in order to solve most of the above problems. This in turn causes more problems. This invention provides a monolithic solution to all the above problems.
The state of the art of error detection and correction apparatus are well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. patents:
U.S. Pat. No. 3,644,902 issued to Beausoleil on Feb. 22, 1972;
U.S. Pat. No. 4,335,459 issued to Miller on June 15, 1982; and
U.S. Pat. No. 4,488,298 issued to Bond et al on Dec. 11, 1984.
U.S. Pat. No. 3,644,902, Beausoleil, discloses a memory having circuits for correcting single errors in a word read from the memory with means to reconfigure the memory so that a configuration having a double, uncorrectable, error is changed to a configuration having two single, correctable errors.
U.S. Pat. No. 4,335,459, Miller, discusses the production yield and reliability of random access integrated circuit memory chips which are greatly increased by providing a memory capacity greater than the nominal capacity of the chip and providing error correction circuitry on the chip.
U.S. Pat. No. 4,488,298, Bond et al, relates to a fault alignment exclusion method and apparatus which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The present invention is directed to an error detection and correction apparatus which is intended to satisfy the above-mentioned prior art problems.